| ❯ bat -r260:350 build/wally/job0/syn/0/inputs/wallypipelinedcorewrapper.v
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| ───────┬─────────────────────────────────────────────────────────────────────────────────────────────────────────
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| │ File: build/wally/job0/syn/0/inputs/wallypipelinedcorewrapper.v
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| ───────┼─────────────────────────────────────────────────────────────────────────────────────────────────────────
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| 260 │ .clk(clk),
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| 261 │ .reset(reset),
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| 262 │ .MTimerInt(MTimerInt),
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| 263 │ .MExtInt(MExtInt),
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| 264 │ .SExtInt(SExtInt),
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| 265 │ .MSwInt(MSwInt),
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| 266 │ .MTIME_CLINT(MTIME_CLINT),
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| 267 │ .HRDATA(HRDATA),
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| 268 │ .HREADY(HREADY),
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| 269 │ .HRESP(HRESP),
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| 270 │ .HCLK(HCLK),
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| 271 │ .HRESETn(HRESETn),
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| 272 │ .HADDR(HADDR),
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| 273 │ .HWDATA(HWDATA),
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| 274 │ .HWSTRB(HWSTRB),
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| 275 │ .HWRITE(HWRITE),
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| 276 │ .HSIZE(HSIZE),
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| 277 │ .HBURST(HBURST),
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| 278 │ .HPROT(HPROT),
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| 279 │ .HTRANS(HTRANS),
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| 280 │ .HMASTLOCK(HMASTLOCK),
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| 281 │ .ExternalStall(ExternalStall)
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| 282 │ );
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| 283 │ endmodule
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| 284 │ module cache (
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| 285 │ clk,
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| 286 │ reset,
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| 287 │ Stall,
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| 288 │ FlushStage,
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| 289 │ CacheRW,
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| 290 │ FlushCache,
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| 291 │ InvalidateCache,
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| 292 │ CMOpM,
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| 293 │ NextSet,
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| 294 │ PAdr,
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| 295 │ ByteMask,
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| 296 │ WriteData,
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| 297 │ CacheCommitted,
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| 298 │ CacheStall,
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| 299 │ ReadDataWord,
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| 300 │ CacheMiss,
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| 301 │ CacheAccess,
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| 302 │ SelHPTW,
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| 303 │ CacheBusAck,
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| 304 │ SelBusBeat,
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| 305 │ BeatCount,
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| 306 │ FetchBuffer,
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| 307 │ CacheBusRW,
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| 308 │ CacheBusAdr
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| 309 │ );
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| 310 │ parameter [4216:0] P = 0;
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| 311 │ parameter PA_BITS = 0;
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| 312 │ parameter LINELEN = 0;
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| 313 │ parameter NUMSETS = 0;
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| 314 │ parameter NUMWAYS = 0;
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| 315 │ parameter LOGBWPL = 0;
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| 316 │ parameter WORDLEN = 0;
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| 317 │ parameter MUXINTERVAL = 0;
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| 318 │ parameter READ_ONLY_CACHE = 0;
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| 319 │ input wire clk;
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| 320 │ input wire reset;
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| 321 │ input wire Stall;
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| 322 │ input wire FlushStage;
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| 323 │ input wire [1:0] CacheRW;
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| 324 │ input wire FlushCache;
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| 325 │ input wire InvalidateCache;
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| 326 │ input wire [3:0] CMOpM;
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| 327 │ input wire [11:0] NextSet;
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| 328 │ input wire [PA_BITS - 1:0] PAdr;
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| 329 │ input wire [(WORDLEN - 1) / 8:0] ByteMask;
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| 330 │ input wire [WORDLEN - 1:0] WriteData;
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| 331 │ output wire CacheCommitted;
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| 332 │ output wire CacheStall;
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| 333 │ output wire [WORDLEN - 1:0] ReadDataWord;
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| 334 │ output wire CacheMiss;
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| 335 │ output wire CacheAccess;
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| 336 │ input wire SelHPTW;
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| 337 │ input wire CacheBusAck;
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| 338 │ input wire SelBusBeat;
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| 339 │ input wire [LOGBWPL - 1:0] BeatCount;
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| 340 │ input wire [LINELEN - 1:0] FetchBuffer;
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| 341 │ output wire [1:0] CacheBusRW;
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| 342 │ output wire [PA_BITS - 1:0] CacheBusAdr;
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| 343 │ localparam LINEBYTELEN = LINELEN / 8;
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| 344 │ localparam OFFSETLEN = $clog2(LINEBYTELEN);
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| 345 │ localparam SETLEN = $clog2(NUMSETS);
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| 346 │ localparam SETTOP = SETLEN + OFFSETLEN;
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| 347 │ localparam TAGLEN = PA_BITS - SETTOP;
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| 348 │ localparam FLUSHADRTHRESHOLD = NUMSETS - 1;
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| 349 │ wire SelAdrData;
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| 350 │ wire SelAdrTag;
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| ───────┴─────────────────────────────────────────────────────────────────────────────────────────────────────────
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