❯ bat -r260:350 build/wally/job0/syn/0/inputs/wallypipelinedcorewrapper.v
───────┬─────────────────────────────────────────────────────────────────────────────────────────────────────────
       │ File: build/wally/job0/syn/0/inputs/wallypipelinedcorewrapper.v
───────┼─────────────────────────────────────────────────────────────────────────────────────────────────────────
 260   │         .clk(clk),
 261   │         .reset(reset),
 262   │         .MTimerInt(MTimerInt),
 263   │         .MExtInt(MExtInt),
 264   │         .SExtInt(SExtInt),
 265   │         .MSwInt(MSwInt),
 266   │         .MTIME_CLINT(MTIME_CLINT),
 267   │         .HRDATA(HRDATA),
 268   │         .HREADY(HREADY),
 269   │         .HRESP(HRESP),
 270   │         .HCLK(HCLK),
 271   │         .HRESETn(HRESETn),
 272   │         .HADDR(HADDR),
 273   │         .HWDATA(HWDATA),
 274   │         .HWSTRB(HWSTRB),
 275   │         .HWRITE(HWRITE),
 276   │         .HSIZE(HSIZE),
 277   │         .HBURST(HBURST),
 278   │         .HPROT(HPROT),
 279   │         .HTRANS(HTRANS),
 280   │         .HMASTLOCK(HMASTLOCK),
 281   │         .ExternalStall(ExternalStall)
 282   │     );
 283   │ endmodule
 284   │ module cache (
 285   │     clk,
 286   │     reset,
 287   │     Stall,
 288   │     FlushStage,
 289   │     CacheRW,
 290   │     FlushCache,
 291   │     InvalidateCache,
 292   │     CMOpM,
 293   │     NextSet,
 294   │     PAdr,
 295   │     ByteMask,
 296   │     WriteData,
 297   │     CacheCommitted,
 298   │     CacheStall,
 299   │     ReadDataWord,
 300   │     CacheMiss,
 301   │     CacheAccess,
 302   │     SelHPTW,
 303   │     CacheBusAck,
 304   │     SelBusBeat,
 305   │     BeatCount,
 306   │     FetchBuffer,
 307   │     CacheBusRW,
 308   │     CacheBusAdr
 309   │ );
 310   │     parameter [4216:0] P = 0;
 311   │     parameter PA_BITS = 0;
 312   │     parameter LINELEN = 0;
 313   │     parameter NUMSETS = 0;
 314   │     parameter NUMWAYS = 0;
 315   │     parameter LOGBWPL = 0;
 316   │     parameter WORDLEN = 0;
 317   │     parameter MUXINTERVAL = 0;
 318   │     parameter READ_ONLY_CACHE = 0;
 319   │     input wire clk;
 320   │     input wire reset;
 321   │     input wire Stall;
 322   │     input wire FlushStage;
 323   │     input wire [1:0] CacheRW;
 324   │     input wire FlushCache;
 325   │     input wire InvalidateCache;
 326   │     input wire [3:0] CMOpM;
 327   │     input wire [11:0] NextSet;
 328   │     input wire [PA_BITS - 1:0] PAdr;
 329   │     input wire [(WORDLEN - 1) / 8:0] ByteMask;
 330   │     input wire [WORDLEN - 1:0] WriteData;
 331   │     output wire CacheCommitted;
 332   │     output wire CacheStall;
 333   │     output wire [WORDLEN - 1:0] ReadDataWord;
 334   │     output wire CacheMiss;
 335   │     output wire CacheAccess;
 336   │     input wire SelHPTW;
 337   │     input wire CacheBusAck;
 338   │     input wire SelBusBeat;
 339   │     input wire [LOGBWPL - 1:0] BeatCount;
 340   │     input wire [LINELEN - 1:0] FetchBuffer;
 341   │     output wire [1:0] CacheBusRW;
 342   │     output wire [PA_BITS - 1:0] CacheBusAdr;
 343   │     localparam LINEBYTELEN = LINELEN / 8;
 344   │     localparam OFFSETLEN = $clog2(LINEBYTELEN);
 345   │     localparam SETLEN = $clog2(NUMSETS);
 346   │     localparam SETTOP = SETLEN + OFFSETLEN;
 347   │     localparam TAGLEN = PA_BITS - SETTOP;
 348   │     localparam FLUSHADRTHRESHOLD = NUMSETS - 1;
 349   │     wire SelAdrData;
 350   │     wire SelAdrTag;
───────┴─────────────────────────────────────────────────────────────────────────────────────────────────────────