| `timescale 1ns/1ns
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| module mod( input reg [15:0] op1, op2, input reg clock, output reg [15:0] out);
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| always @(posedge clock) begin
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| #1 out = op1 + op2;
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| end
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| endmodule
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| module tb;
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| reg [15:0] op1 = 'h0x1111;
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| reg [15:0] op2 = 'h0x2222;
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| reg [15:0] out;
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| reg clock = 0;
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| mod mod1(.op1(op1), .op2(op2), .out(out), .clock(clock));
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| initial begin
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| $dumpfile("test.vcd");
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| $dumpvars();
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| $monitor("clock = %d, op1=0x%h8, op2=0x%h8, out = 0x%h8", clock, op1, op2, out);
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| #30 $finish();
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| end
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| always begin
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| #1 clock = ~clock; // posedge
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| #1 op1 = op2 * 3;
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| #1 clock = ~clock;
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| #1 op2 = op1 - 2*op2;
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| #1 clock = ~clock; // posedge
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| end
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| endmodule
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