`timescale 1ns/1ns
module mod( input reg [15:0] op1, op2, input reg clock, output reg [15:0] out);
    always @(posedge clock) begin
        #1 out = op1 + op2;
    end
endmodule
module tb;
    reg [15:0] op1 = 'h0x1111;
    reg [15:0] op2 = 'h0x2222;
    reg [15:0] out;
    reg clock = 0;
    mod mod1(.op1(op1), .op2(op2), .out(out), .clock(clock));
    initial begin  
        $dumpfile("test.vcd");
        $dumpvars();
        $monitor("clock = %d, op1=0x%h8, op2=0x%h8, out = 0x%h8", clock, op1, op2, out);
        #30 $finish();        
    end
    always begin        
        #1 clock = ~clock; // posedge
        #1 op1 = op2 * 3;
        #1 clock = ~clock;
        #1 op2 = op1 - 2*op2;
        #1 clock = ~clock; // posedge
    end
endmodule