$date
	Fri Mar 28 15:46:13 2025
$end
$version
	Icarus Verilog
$end
$timescale
	1ns
$end
$scope module tb $end
$var wire 16 ! out [15:0] $end
$var reg 1 " clock $end
$var reg 16 # op1 [15:0] $end
$var reg 16 $ op2 [15:0] $end
$scope module mod1 $end
$var wire 1 " clock $end
$var wire 16 % op1 [15:0] $end
$var wire 16 & op2 [15:0] $end
$var reg 16 ' out [15:0] $end
$upscope $end
$upscope $end
$enddefinitions $end
$comment Show the parameter values. $end
$dumpall
$end
#0
$dumpvars
bx '
b10001000100010 &
b1000100010001 %
b10001000100010 $
b1000100010001 #
0"
bx !
$end
#1
1"
#2
b1000100010001000 !
b1000100010001000 '
b110011001100110 #
b110011001100110 %
#3
0"
#5
1"228, out = 0x88888
clock = 0, op1=0x66668, op2=0x22228, out = 0x88888
clock = 1, op1=0x66668, op2=0x22228, out = 0x88888
clock = 0, op1=0x66668, op2=0x22228, out = 0x88888
#6
0"
#8
1"
#10
0"
#11
1"
#13
0"
#15
1"
#16
0"
#18
1"
#20
0"
#21
1"
#23
0"
#25
1"
#26
0"
#28
1"
#30
0"