| static int video_cc_sm8550_probe(struct platform_device *pdev)
|
| {
|
| if (of_device_is_compatible(pdev->dev.of_node, "qcom,sm8650-videocc")) {
|
| video_cc_pll0_config.l = 0x1e;
|
| video_cc_pll0_config.alpha = 0xa000;
|
| video_cc_pll1_config.l = 0x2b;
|
| video_cc_pll1_config.alpha = 0xc000;
|
| video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_sm8650;
|
| video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_sm8650;
|
| video_cc_sm8550_clocks[VIDEO_CC_MVS0_SHIFT_CLK] = &video_cc_mvs0_shift_clk.clkr;
|
| video_cc_sm8550_clocks[VIDEO_CC_MVS0C_SHIFT_CLK] = &video_cc_mvs0c_shift_clk.clkr;
|
| video_cc_sm8550_clocks[VIDEO_CC_MVS1_SHIFT_CLK] = &video_cc_mvs1_shift_clk.clkr;
|
| video_cc_sm8550_clocks[VIDEO_CC_MVS1C_SHIFT_CLK] = &video_cc_mvs1c_shift_clk.clkr;
|
| video_cc_sm8550_clocks[VIDEO_CC_XO_CLK_SRC] = &video_cc_xo_clk_src.clkr;
|
|
|
| /* Sleep clock offset changed to 0x8150 on SM8650 */
|
| video_cc_sm8550_critical_cbcrs[2] = 0x8150;
|
| }
|
|
|
| if (of_device_is_compatible(pdev->dev.of_node, "qcom,x1e80100-videocc")) {
|
| video_cc_pll0_config.l = 0x1e;
|
| video_cc_pll0_config.alpha = 0x0000;
|
| video_cc_pll1_config.l = 0x2b;
|
| video_cc_pll1_config.alpha = 0xc000;
|
| video_cc_mvs0_clk_src.freq_tbl = ftbl_video_cc_mvs0_clk_src_x1e80100;
|
| video_cc_mvs1_clk_src.freq_tbl = ftbl_video_cc_mvs1_clk_src_x1e80100;
|
| }
|
|
|
| return qcom_cc_probe(pdev, &video_cc_sm8550_desc);
|
| }
|