| diff --git a/src/nouveau/vulkan/nvk_cmd_dispatch.c b/src/nouveau/vulkan/nvk_cmd_dispatch.c
|
| index a96bd230eb9..a425bdc438a 100644
|
| --- a/src/nouveau/vulkan/nvk_cmd_dispatch.c
|
| +++ b/src/nouveau/vulkan/nvk_cmd_dispatch.c
|
| @@ -510,7 +510,7 @@ nvk_CmdDispatchIndirect(VkCommandBuffer commandBuffer,
|
| struct nv_push *p;
|
| if (nvk_cmd_buffer_compute_cls(cmd) >= TURING_A) {
|
| p = nvk_cmd_buffer_push(cmd, 14);
|
| - P_IMMD(p, NVC597, SET_MME_DATA_FIFO_CONFIG, FIFO_SIZE_SIZE_4KB);
|
| + //P_IMMD(p, NVC597, SET_MME_DATA_FIFO_CONFIG, FIFO_SIZE_SIZE_4KB);
|
| P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_DISPATCH_INDIRECT));
|
| P_INLINE_DATA(p, dispatch_addr >> 32);
|
| P_INLINE_DATA(p, dispatch_addr);
|
| diff --git a/src/nouveau/vulkan/nvk_cmd_draw.c b/src/nouveau/vulkan/nvk_cmd_draw.c
|
| index d90dd9d5651..a98a6924550 100644
|
| --- a/src/nouveau/vulkan/nvk_cmd_draw.c
|
| +++ b/src/nouveau/vulkan/nvk_cmd_draw.c
|
| @@ -138,8 +138,8 @@ nvk_push_draw_state_init(struct nvk_queue *queue, struct nv_push *p)
|
| free(dw);
|
| }
|
|
|
| - if (pdev->info.cls_eng3d >= TURING_A)
|
| - P_IMMD(p, NVC597, SET_MME_DATA_FIFO_CONFIG, FIFO_SIZE_SIZE_4KB);
|
| +// if (pdev->info.cls_eng3d >= TURING_A)
|
| +// P_IMMD(p, NVC597, SET_MME_DATA_FIFO_CONFIG, FIFO_SIZE_SIZE_4KB);
|
|
|
| /* Enable FP helper invocation memory loads
|
| *
|
| @@ -153,7 +153,7 @@ nvk_push_draw_state_init(struct nvk_queue *queue, struct nv_push *p)
|
| * dEQP-VK.subgroups.vote.frag_helper.subgroupallequal_bvec2_fragment will
|
| * occasionally fail.
|
| */
|
| - if (pdev->info.cls_eng3d >= MAXWELL_B) {
|
| + if (0 && pdev->info.cls_eng3d >= MAXWELL_B) {
|
| unsigned reg = pdev->info.cls_eng3d >= VOLTA_A ? 0x419ba4 : 0x419f78;
|
| P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_SET_PRIV_REG));
|
| P_INLINE_DATA(p, 0);
|
| @@ -207,7 +207,7 @@ nvk_push_draw_state_init(struct nvk_queue *queue, struct nv_push *p)
|
| *
|
| * This clears bit 14 of gr_gpcs_tpcs_sms_hww_warp_esr_report_mask
|
| */
|
| - if (pdev->info.cls_eng3d >= MAXWELL_B) {
|
| + if (0 && pdev->info.cls_eng3d >= MAXWELL_B) {
|
| unsigned reg = pdev->info.cls_eng3d >= VOLTA_A ? 0x419ea8 : 0x419e44;
|
| P_1INC(p, NV9097, CALL_MME_MACRO(NVK_MME_SET_PRIV_REG));
|
| P_INLINE_DATA(p, 0);
|
| diff --git a/src/nouveau/winsys/nouveau_device.c b/src/nouveau/winsys/nouveau_device.c
|
| index 925df476be9..d0156d9a154 100644
|
| --- a/src/nouveau/winsys/nouveau_device.c
|
| +++ b/src/nouveau/winsys/nouveau_device.c
|
| @@ -51,6 +51,12 @@ name_for_chip(uint32_t dev_id,
|
| static uint8_t
|
| sm_for_chipset(uint16_t chipset)
|
| {
|
| + if (chipset >= 0x1b0)
|
| + return 104;
|
| + else
|
| + if (chipset >= 0x1a0)
|
| + return 100;
|
| + else
|
| if (chipset >= 0x190)
|
| return 89;
|
| // GH100 is older than AD10X, but is SM90
|